1. Field of the Invention
The present invention relates to an output stage, and in particular relates to an output stage for controlling slew rate and voltage level.
2. Description of the Related Art
An output stage implemented in a chip is a common interface circuit, which is like a buffer device between core circuits of the chip and external circuits or other chips. The output stage can eliminate negative effect caused by interference from loads outside of the chip. Generally, the output stage has a good self-protection mechanism and only an appropriate amount of current driving ability. However, loads driven by the output stage may vary sharply. Even so, an output waveform with high accuracy is still necessary. Therefore, an improved output stage is required.
FIG. 1 is a diagram showing a conventional device for controlling the slew rate of an output signal. In FIG. 1, an input signal is input to the slew rate control logic 11 and output from a plurality of inverters such as inverter 12. The high voltage level VIH and low voltage level VIL can be programmed by the first programmable regulator 13 and the second programmable regulator 14. The inverters 12 are not ideal switching elements and they have particular on-resistances which will affect the transition time of a logic level, i.e. the slew rate of the logic level. However, arranging parallel inverters may vary on-resistances; thereby changing the slew rate of the output signal.
When loads driven by the output signal vary, the voltage provided by the first programmable regulator 13 or the second programmable regulator 14 will be different from to voltage applied to loads. In order to reduce the voltage differences between the loads and the programmable regulators, the sizes of the inverters have to be increased. Unfortunately, the size increments of the inverters magnify parasitical capacitances in the circuit such that the operative speed of the device is lowered. Additionally, the on-resistances of the inverters will cause non-linear effect due to different load voltages such that the waveform of the output signal is distorted. Moreover, waveform distortion of the output signal results when controlling dead time of a PMOS and an NMOS.